The complexity of leading-edge VLSI products (as defined by the numberof transistors on a chip) increases exponentially with time because ofthe underlying semicondutor technology and historical trends. It hasbecome possible to design entire systems onto a single chip, commonlyknown as System-on-Chip (SoC). The difficulty of the design and testtasks for such SoCs is currently being accelerated and limits ourability to fully utilize new fabrication techniques, a problem known asthe design and test crisis. To overcome this crisis, a breakthrough indesign and test technologies will be needed. Core-based system-on-chipdesign strategies with automated high-level synthesis for cores is apotential means of overcoming the VLSI design complexities. High-leveltestability designs are essential in order to minimize test complexitywithout affecting area or performance. Automated generation ofoptimized test architecture for core-based SoCs is also an essentialmeans of reducing the time-to-market and design and test cost for VLSIproducts. We are currently focusing on research into a high-levelsynthesis of high performance and high testability VLSI circuits aswell as designs for testability at the RT (register-transfer) level andlogic level, based on not only external test but also BIST (built-inself-test). We are also focusing on research of a global design fortest methodology and optimization technique for testing core-basedSoCs. Other ongoing projects on VLSI design and testing includetheoretical research on sequential circuits with combinational testgeneration complexity, super-efficient and robust test generationalgorithms for ultra-large-scale combinational circuits, parallelprocessing for test generation, and hardware security.

Logic Design Theory / Digital Systems Design and Test / VLSI CAD

This area includes research into design and test forsystems-on-a-chip, high-level synthesis for testability, logicsynthesis for testability, design for testability, test synthesis, hardware security, secure and testable design, testgeneration, fault simulation, parallel processing for CAD, etc.

Highly Reliable Design / Fault Tolerant Computing

Includes hardware security, design for security, highly reliable design for VLSIs, built in self test forVLSIs, high reliable multi processor systems, fault tolerant systems, hardware security, secure and testable design, etc.

Hardware/Software Co-Design

Includes CAD for H/S co-design, hardware algorithms, design and test of reconfigurable hardwares (FPGAs), etc.