IEEE Fellow Award, January 1989 [JPG] "for contributions to research and development on testing of large integrated circuits."
IEEE Computer Society Certificate of Appreciation Award , October 1991 "for many years of dedicated service on the Asian Subcommittee of the Program Committee of the International Test Conference."
IEEE Computer Society Meritorious Service Award , November 1996 [JPG] "for many years of dedicated service in guiding and participating in the TTTC Asian Activities and the Asian Test Symposium."
IEEE Computer Society Golden Core Member Award , December 1997 [JPG] "as one of the distinguished core of dedicated volunteers and staffwhose leadership and services have made the IEEE Computer Society theworld's preminent association of computing professionals."
IEEE Computer Society Certificate of Appreciation Award , October 2000 "for founding and chairing the IEEE RT-Level ATPG and DFT Workshop."
IEICE Fellow , September 2001 [JPG] "for contributions to pioneering research on logic design theory and desgin automation."
IEEE Computer Society Certificate of Appreciation Award , November 2001 "for dedicated service to the Asian Test Symposium and the Asian Activities of the IEEE TTTC."
IEEE Computer Society Outstanding Contribution Award , November 2001 [JPG] "for providing outstanding contributions to TTTC Asian Test Symposium (ATS) for more than ten years."
IEICE ISS 2001 Year Paper Award , September 2002 [JPG] "Combinational Test Generation Complexity and Non Scan Design for Test Method" for 4 papers in IEICE Trans. D-I.
IPSJ Fellow , March 2004 [JPG] "for contributions to pioneering research on logic design theory and desgin automation."
IEEE ATS'02 Best Paper Award (IEEE Asian Test Symposium 2002) , November 2004 Erik Larsson, Klas Arvidsson, Hideo Fujiwara and Zebo Peng,"Integrated Test Scheduling, Test Parallelization and TAM Design,"Proc. of IEEE the 11th Asian Test Symposium (ATS'02),pp. 397-404, Nov. 2002.
IEEE WRTLT'03 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2003) , November 2004 Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara,"An approach to non-scan design for delay fault testability of controllers,"Digest of Papers IEEE the 4th Workshop on RTL and High Level Testing (WRTLT '03),pp. 79-85, Nov. 2003.
IEEE Computer Society Continuing Service Award , November 200 5 "for serving the ATS Steering Committee as Chair from 2001 to 2004"
IEEE Computer Society Meritorious Service Award , November 2005 [JPG] "for significant services as TTTC Asian & Pacific Group Chair in 2004 and 2005"
IEEE DELTA'06 Best Paper Award (Third IEEE International Workshop on Electronic Design, Test & Applications, DELTA 2006) , January 2006 Michel Renovell, Mariane Comte, Satoshi Ohtake and Hideo Fujiwara,"Electrical Behavior of GOS Fault affected Domino Logic Cell,"Third IEEE International Workshop on Electronic Design, Test & Applications (DELTA 2006), pp. 183-189, Jan. 2006
IEEE WRTLT'05 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2005), November 2006 Masato Nakazato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara,"Acceleration of Test Generation for Sequential Circuits UsingKnowledge Obtained from Synthesis for Testability," Proc. of IEEE 6thWorkshop on RTL and High Level Testing (WRTLT'05), pp. 50-60, June2005.
IEEE WRTLT'07 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2007), November 2008 Yuki Yoshikawa, Satoshi Ohtake and Hideo Fujiwara,"RTL don’t care path identification and synthesis for transforming don’t care paths into false paths,"Digest of Papers IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07), pp. 9-15, October 2007.
IEEE Computer Society Outstanding Contribution Award , May 2009 [JPG] "for significant services as TTTC Asian & Pacific Group Chair for more than four years"
IEEE WRTLT'08 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2008), November 2009 Hideo Fujiwara, Chia Yee Ooi, and Yuki Shimizu, "Enhancement of Test Environment Generation for Assignment Decision Diagrams," Digest of Papers IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08), pp.45-50, November 2009.
IEEE WRTLT'09 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2009), November 2011 Marie E. J. Obien and Hideo Fujiwara, "A DFT Method for Functional Scan at RTL," 10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), pp. 6-15, Nov. 2009.
IEEE WRTLT'11 Best Paper Award (IEEE Twelfth Workshop on RTL and High Level Testing 2011), November 2012 Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'Ameri, and Hideo Fujiwara, "Built-in Self-Test for Functional Register-Transfer Level using Assignment Decision Diagram," IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT'11), pp. 9-15, Nov. 2011.
IEEE WRTLT'14 Best Paper Award (IEEE Fifteenth Workshop on RTL and High Level Testing 2014), November 2015 Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara, "A Scheduling Method for Hierarchical Testability Using Results of Test Environment Generation," 15th IEEE Workshop on RTL and High Level Testing (WRTLT'14), Nov. 2014.
IEEE Computer Society TTTC Outstanding Contribution Award , Nov. 21, 2016. [JPG] "for serving 3rd ATS General Chair, November 15-17, 1994."
IEEE 25th Asian Test Symposium Certificate of Appreciation, Nov. 21, 2016. "for contribution to the 25th Anniversary Panel Session."
IEEE Computer Society TTTC ATS Most Contribution Author Award, Nov. 21, 2016.[JPG]
